1. Field of Invention
The present invention relates generally to the field of circuit board testing. More specifically, the present invention is related to a method and apparatus to remove signal interference created by long wires used during testing circuit boards by systems using wrapped wire bed-of-nails fixtures.
2. Discussion of Prior Art
In-circuit and other types of testing have typically used a "bed-of-nails" to contact individual circuit traces (nodes) on the bottom and/or top of populated printed circuit boards in order to test or measure individual components or electrical functions of the board. The "nails" are spring loaded 46 pins with a sharp point 45 that contacts the circuit board 30 and typically plug into a socket receptacle 47 with a wire-wrap pin 48 on the other end. The nails are held in place by the sockets which are held in place by an insulating material 31. Each bed-of-nails fixture is unique to its respective circuit board and has anywhere from a few nails to a few thousand nails. The circuit board is brought into contact with the nails by either a vacuum that brings the board down onto the pins and compresses the springs, by a pneumatic or mechanical device that pushes the circuit board into contact with the nails, or by moving bed-of-nails that close on the circuit board from the top and/or bottom.
The wire-wrap pin of each socket receptacle is wired to various types of connector blocks 40 at the fixture receiver interface 32/33, with wires 22 that are from one to three feet in length. Another set of wires 23, also one to three feet in length, connect the connector block in the receiver 41 to the test electronics 35. The second set of wires connect first to a set of relays 36 that switch the wires, and their respective pins, to the tester electronics 35 located within the remote testing unit 20. Therefore, when the bed-of-nails fixture is in contact with the board, there is a wire connected to each circuit trace that is two to six feet in length. For many circuit boards and tests, these wires do not interfere with the testing of the board. However, high frequency circuit boards (high speed digital, wireless, CATV and other high frequency products) usually have very small value components in complex circuits making them very difficult to measure.
Lengths of wire associated with a bed-of-nails fixture are in contact with the board, making testing even more difficult. These extra lengths of wire can add capacitance and/or inductance, or act like antennas, making accurate measurements impossible. One solution has been to use a two stage fixture which first makes contact with a minimum number of pins in order to make tests on the smaller or more sensitive nodes of the circuit board. Then, a second actuation brings the board into contact with all of the nails to complete the testing. The main disadvantage of this method is that many wires are still connected to the circuit card during the first stage of testing. Also, two stage fixtures are complex and more costly.
In order to provide background information so that the invention may be completely understood and appreciated in its proper context, reference may be made to a number of prior art patents as follows:
The patent to Marek et al. (U.S. Pat. No. 5,187,430), assigned to Compaq Computer Corporation, describes a Method and Apparatus for Determining Nets Among Nodes in a Circuit Board. The circuit board 10 is the Board-Under-Test (BUT) and the relay switch box 20 connects the capacitance measuring meter 31, potential 38, current 39 and ground 40 lines to the measurement lines connected to the various reference planes of the BUT. The computer 34 properly sets relays 21 which effects the application of the appropriate stimulus (column 6, lines 55-60). The purpose of this patent is to measure or verify the number of "nets" of a bare or unstuffed or unpopulated circuit board. The "Relay Switch Box" referred to in the patent is not related to the switch of the present invention.
The patent to Berger et al. (U.S. Pat. No. 5,126,953) describes a Printed Circuit Board Assembly Tester. The switch matrix 12 is controlled by a computer 16 to cause the switch matrix to connect the "nails" of fixture 11 to a measuring instrument 20 (column 4, lines 14-16). A wire-wrap.TM. connection 36 connects to a "nail" in the universal grid fixture 10. The patent suggests the use of classic in-circuit test techniques using CMOS switches instead of reed relays in the switch matrix. The patent also refers to the use of a bed-of-nails fixture and wire-wrap pins, the general environment of the present invention.
The patent to Gonzalez et al. (U.S. Pat. No. 4,857,833), assigned to Teradyne, Inc., describes the Diagnosis of Faults on Circuit Board. The measurement apparatus 16 includes a relay matrix 45 which connects line 48 to line 50 to the measurement system 46. The bed of nails 14 then makes electrical contact with the BUT to perform passive voltage measurements. The patent also refers to the use of a bed-of-nails fixture, the general environment of the present invention.
The patent to Berry (U.S. Pat. No. 2,982,913), assigned to Western Electric Company, Inc., describes Test Sets. The test apparatus includes a pair of relays for each pair of corresponding terminals of the test network and the master network (column 1, lines 42-46). The high speed switching relay 23 has an operating coil 32 which is energized by power source 13. The high speed relay 23 has normally open contacts 22 until energized (column 2, lines 49-52). This patent relates to the testing of patch panels using lots of relays, the technology of the period, but fails to disclose the present invention.
The patent to Canarutto (U.S. Pat. No. 3,723,867), assigned to Ing. C. Olivetti & C., S.p.A., describes an Apparatus Having a Plurality of Multi-Position Switches for Automatically Testing Electronic Circuit Boards. The apparatus describes an electromechanical or electronic type switch 44 which extends to a measuring instrument 49. The computer selects switches 56 and 57 and connects them with selected generators 66 and 67 for stimulus. This patent offers a general description of in-circuit testing using dated technology.
The patent to Bailey et al. (U.S. Pat. No. 4,714,875), assigned to Mars, Inc., describes a Printed Circuit Board Fault Location System and the patent to Heaton et al. (U.S. Pat. No. 5,103,169), assigned to Texas Instruments Incorporated, describes a Relayless Interconnections in High Performance Signal Paths. These patents provide the teaching of using solid state switches (CMOS and FETS) in place of electromechanical switches to interface the measuring device and stimulating device to the BUT under computer control in a "Bed-of-Nails" test bed. The patent covers a classic in-circuit test system that uses a standard bed-of-nails where the present invention could be used.
The patent to Norimatsu (U.S. Pat. No. 5,252,936), assigned to Hewlett-Packard Company, describes a Reed Relay and Switch Matrix Device Using the Same. A switching operation for conduction between plural measuring devices and plural DUTs is performed with a matrix of reed relay and connecting switches. The purpose of this patent is to eliminate the leakage current associated with a reed relay to improve the measurement accuracy. The relays are contained in a matrix of relays connected by a length of wire to the device under test. The proposed invention would disconnect the length of wire, that can effect other tests, from the DUT or the fixture holding the DUT.
Whatever the precise merits, features, and advantages of the above cited references, none of them achieve or fulfill the purpose of the present invention. Accordingly, it is an object of the present invention to eliminate the inherent problems associated with long testing wires used in electronic testing systems.
It is another object of the present invention to eliminate potential antenna effects of long wires created during testing of high frequency or wireless circuit boards.
It is an additional object of the present invention to increase the accuracy of reading small value electronic components and therefore provide improved test results here before unobtainable. These and other objects are achieved by the detailed description that follows.